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1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash
SST27VF010 / SST27VF020
SST27VF010 / 0205.0V-Read 1Mb / 2Mb (x8) MTP flash memories
Preliminary Specifications
FEATURES:
* Organized as 128K x8 / 256K x8 * 2.7-3.6V Read Operation * Superior Reliability - Endurance: At least 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) - Standby Current: 2 A (typical) * Fast Read Access Time - 70 ns (PLCC or TSOP) - 90 ns (PDIP) * Fast Byte-Program Operation - Byte-Program Time: 15 s (typical) - Chip Program Time: 2 seconds (typical) for SST27VF010 4 seconds (typical) for SST27VF020 * Electrical Erase Using Programmer - Does not require UV source - Chip-Erase Time: 100 ms (typical) * JEDEC Standard Byte-wide EPROM Pinouts * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 32-pin PDIP
PRODUCT DESCRIPTION
The SST27VF010/020 are 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12V power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Byte-Program, the SST27VF010/020 provide a Byte-Program time of 15 s. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST27VF010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27VF010/020 are offered in 32-pin PDIP 32-lead PLCC, and 32-lead TSOP packages. See , Figures 1, 2, and 3 for pin assignments.
Device Operation
The SST27VF010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical Erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27VF010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 2 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
(c)2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
Byte-Program Operation
The SST27VF010/020 are programmed by using an external programmer. The programming mode for SST27VF010/020 is activated by asserting 11.4-12.0V on VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (PGM# pin low for SST27VF010/020) of 15 s. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed.
pins are "don't care". The falling edge of CE# (PGM# for SST27VF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 9 for the flowchart.
Product Identification Mode
The Product Identification mode identifies the devices as the SST27VF010 or SST27VF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27VF010/020, the programming equipment must force VH (11.4-12.6V) on address A9 with VPP pin at VDD (2.7-3.6V) or VSS. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST27VF010 SST27VF020 0001H 0001H A9H AAH
T1.0 1251
Chip-Erase Operation
The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27VF010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (PGM# pin for SST27VF010/020). In order to activate the Erase mode for SST27VF010/020, the 11.4-12.6V is applied to the A9 pin, 11.4-12.0V is applied to the VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. All other address and data FUNCTIONAL BLOCK DIAGRAM OF THE SST27VF010/020
Data BFH
0000H
X-Decoder
SuperFlash Memory
AMS - A0
Address Buffer Y-Decoder
CE# OE# A9 VPP PGM#
I/O Buffers Control Logic DQ7 - DQ0
1251 B1.0
AMS = A17 for SST27VF020, A16 for SST27VF010
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
SST27VF010 SST27VF020
PGM# PGM#
VDD
VPP
A12
A15
A16
VDD
VPP
A12
A15
A16
SST27VF010/020 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 SST27VF010/020 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20
NC SST27VF010/020 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
1251 32-plcc P1.0
32-lead PLCC Top View
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
SST27VF020 SST27VF010
A11 A9 A8 A13 A14 A17 PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1251 32-tsop P2.0
DQ6
A17
SST27VF010/020
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Standard Pinout Top View Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM
X
14MM)
(c)2003 Silicon Storage Technology, Inc.
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
SST27SV010/020 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SST27VF010 SST27VF020 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
1251 32-pdip P3.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
(c)2003 Silicon Storage Technology, Inc.
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 CE# OE# VPP VDD VSS NC Pin Name Address Inputs Data Input/output Chip Enable Output Enable Power Supply for Program or Erase Power Supply Ground No Connection Unconnected pins.
T2.0 1251
Functions To provide memory addresses To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low To gate the data output buffers during Read operation High voltage pin during Chip-Erase and programming operation 11.4-12.0V To provide 3.0V supply (2.7-3.6V)
1. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020
TABLE 3: OPERATION MODES SELECTION
Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification CE# VIL VIL VIL VIH VIL VIH VIL OE# VIL VIH VIH X VIH X VIL PGM# X1 X VIL X VIL X X A9 AIN X AIN X VH X VH VPP VDD or VSS VDD or VSS VPPH VDD or VSS VPPH VPPH VDD or VSS DQ DOUT High Z DIN High Z High Z High Z Manufacturer's ID (BFH) Device ID2 Address AIN AIN AIN X X X AMS3 - A1=VIL, A0=VIL AMS3 - A1=VIL, A0=VIH
T3.0 1251
1. X can be VIL or VIH, but no other value. 2. Device ID = A9H for SST27VF010 and AAH for SST27VF020 3. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020 Note: VPPH = 11.4-12.0V, VH = 11.4-12.6V
(c)2003 Silicon Storage Technology, Inc.
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Ambient Temp 0C to +70C VDD 2.7-3.6V VPP 11.4-12.0V
AC CONDITIONS
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 7 and 8
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V, VPP=VDD OR VSS (Ta = 0C to +70C (Commercial))
Limits Symbol Parameter IDD VDD Read Current 15 IPPR VPP Read Current 100 ISB ILI ILO VIL VIH VIHC VOL VOH IH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Supervoltage Current for A9 VDD-0.3 200 0.7VDD VDD-0.3 0.2 15 1 10 0.8 A A A A V V V V V A mA Min Max Units Test Conditions Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max CE#=OE#=VIL, all I/Os open Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max, VPP=VDD CE#=OE#=VIL, all I/Os open CE#=VDD-0.3, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min CE#=OE#=VIL, A9=VH Max
T4.0 1251
TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V, VPP = VPPH (Ta=25C5C)
Limits Symbol Parameter IDD IPP ILI ILO VH IH VPPH VDD Erase or Program Current VPP Erase or Program Current Input Leakage Current Output Leakage Current Supervoltage for A9 Supervoltage Current for A9 High Voltage for VPP Pin Min Max Units Test Conditions 20 3 1 10 11.4 12.6 200 11.4 12.0 mA mA A A V A V
T5.0 1251
CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.0V, VDD=VDD Max CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.0V, VDD=VDD Max VIN =GND to VDD, VDD=VDD Max VOUT =GND to VDD, VDD=VDD Max CE#=OE#=VIL, CE#=OE#=VIL, A9=VH Max
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T6.0 1251
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE
Parameter CI/O1 CIN
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 1251
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 1000 100 100
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.0 1251
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
8
1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
(Ta = 0C to +70C (Commercial))
SST27VF010-70 SST27VF020-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 25 25 Min 70 70 70 35 Max
SST27VF010-90 SST27VF020-90 Min 90 90 90 45 0 0 30 30 0 Max Units ns ns ns ns ns ns ns ns ns
T9.0 1251
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TCES TCEH TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase
(Ta = 25C5C)
Min 1 1 1 1 50 1 1 15 100 1 1 1 50 1 1
Max
25 200
Units s s s s ns s s s ms s s s ns s s
T10.0 1251
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
ADDRESS
TRC TAA
CE#
TCE
OE#
TOE
TOLZ
TOHZ TOH DATA VALID TCHZ DATA VALID
DQ7-0
HIGH-Z TCLZ
1251 F04.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT A9) CE#
TCEH
OE# VIH
DQ7-0 VPPH VDD VSS VPPH A9 VIH VIL TART TA9H PGM# TCES
1251 F05.0
TVPS TVPH TPRT TA9S TVR
VPP
TEW
FIGURE 5: CHIP-ERASE TIMING DIAGRAM
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
ADDRESS
ADDRESS VALID
TAH TAS
CE#
TCEH
OE#
VIH
TDS TDH
DQ7-0
HIGH-Z VPPH VDD
DATA VALID
TVPS
VPP PGM#
TPRT
VSS
TPW TVPH
TCES
1251 F06.0
FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM
(c)2003 Silicon Storage Technology, Inc.
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1251 F07.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUTTest VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS
VDD TO TESTER RL HIGH
TO DUT CL RL LOW
1251 F08.0
FIGURE 8: A TEST LOAD EXAMPLE
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
Start
A9 = VH, VPP = VPPH
CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL)
PGM# = VIH
A9 = VIL or VIH
Wait A9 Recovery Time
Read Device
Compare all bytes to FFH Yes
No
Device Passed
Device Failed
1251 F09.0
FIGURE 9: CHIP-ERASE ALGORITHM
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
Start
Erase*
VPP = VPPH
Address = First Location
CE# = VIL, OE# = VIH
Program 15 s pulse (PGM# = VIL)
Increment Address No
Last Address? Yes
Read Device
Compare all bytes to original data Yes
No
Device Passed
Device Failed
1251 F10.0
* See Figure 9
FIGURE 10: BYTE-PROGRAM ALGORITHM
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device SST27VFxxx Speed - XXX Suffix1 XX Suffix2 XX X Environmental Attribute E = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C Minimum Endurance 3 = 1,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density - x8 Organization 020 = 2 Mbit 010 = 1 Mbit Voltage Range V = 2.7-3.6V Product Series 27 = Many-Time Programmable Flash
Valid combinations for SST27VF010 SST27VF010-70-3C-NH SST27VF010-70-3C-NHE SST27VF010-70-3C-WH SST27VF010-70-3C-WHE SST27VF010-90-3C-PH SST27VF010-90-3C-PHE Valid combinations for SST27VF020 SST27VF020-70-3C-NH SST27VF020-70-3C-NHE SST27VF020-70-3C-WH SST27VF020-70-3C-WHE SST27VF020-90-3C-PH SST27VF020-90-3C-PHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447
2 1 32
SIDE VIEW
.112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 BSC .490
.050 BSC .015 Min. .050 BSC .095 .075 .140 .125 .032 .026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
12/03
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
Pin # 1 Identifier
1.05 0.95 0.50 BSC
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
X
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
14MM
(c)2003 Silicon Storage Technology, Inc.
S71251-00-000
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1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020
Preliminary Specifications
32
C L
Pin #1 Identifier
1
.075 .065 Base Plane Seating Plane
1.655 1.645
7 4 PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 BSC .150 .120
.012 .008 .600 BSC
0 15
.080 .070
.065 .045
.022 .016
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH
Revision History
Number 00 Description Date Dec 2003
*
Initial Release
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2003 Silicon Storage Technology, Inc. S71251-00-000 12/03
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